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Sr. Physical Design Engineer - Static Timing Analysis, Annapurna Labs, Cloud Scale Machine Learning at Annapurna Labs (U.S.) Inc.

Annapurna Labs (U.S.) Inc.

Sr. Physical Design Engineer - Static Timing Analysis, Annapurna Labs, Cloud Scale Machine Learning

Santa Clara, CA, USA|

Job Overview

Compensation

Salary

Range $183,000.00 - $247,600.00

Benefits

Health Insurance

Dental Insurance

Vision Insurance

Prescription coverage

Basic Life and AD&D insurance

Supplemental life plans

Employee assistance program

mental health support

Medical advice line

flexible spending accounts

adoption and surrogacy reimbursement

401(k) matching

Paid Time Off

Parental leave

Job Description

Amazon Web Services (AWS) is the world’s most comprehensive and broadly adopted cloud platform, trusted by millions of customers including startups, large enterprises, and government agencies globally. AWS leads the industry in cloud innovation, providing a vast array of foundational and advanced services such as Amazon Simple Storage Service (S3), Amazon Elastic Compute Cloud (EC2), and numerous other cutting-edge offerings that enable businesses to scale and innovate efficiently. The AWS Utility Computing (UC) organization is pivotal in this mission, supporting the development, management, and deployment of services encompassing Compute, Database, Storage, Internet of Things (IoT), Platform, and Productivity Apps. This includes catering to customers with specialized security needs for their cloud environments, ensuring robust, scalable, and secure cloud infrastructure and services.

AWS Utility Computing team continuously pushes the boundaries of what is possible in cloud infrastructure. As a Sr. Physical Design STA Engineer within this team, you will be at the forefront of designing and optimizing the next generation of AWS cloud server platforms. Your work will directly impact the performance, efficiency, and reliability of hardware underpinning AWS’s global data centers and cloud offerings. In this role, you will focus on advanced static timing analysis (STA) for chip design, specifically contributing to the development and optimization of hardware accelerators like AWS Inferentia, a machine learning inference chip built to deliver superior performance at lower cost.

In this fast-paced and intellectually rigorous environment, you will collaborate with leading experts across multiple technology domains. Your expertise in static timing analysis and physical design fundamentals will be critical in enhancing the performance, quality, and cost-effectiveness of AWS’s hardware platforms. This role demands a proactive problem solver who is passionate about leveraging new technologies and methodologies to solve complex design challenges. You will be involved in developing, maintaining, and automating timing analysis flows, writing and validating timing constraints, providing actionable feedback to the engineering teams, and creating strategies to resolve timing issues effectively.

AWS values diversity and inclusion, fostering a culture where innovation thrives through the variety of perspectives and experiences. Employees at AWS enjoy work-life balance, mentorship opportunities, ongoing learning, and career growth supported by an inclusive environment. Amazon offers highly competitive salaries, including sign-on bonuses and restricted stock units, comprehensive benefits such as health insurance, 401(k) matching, paid time off, and parental leave.

This position is based in Cupertino, California, and offers a base salary range from $183,000 to $247,600 annually. Joining AWS means contributing to revolutionary cloud technologies, working alongside a dynamic team dedicated to customer obsession and operational excellence, and being part of one of the most innovative companies in the world.

Job Requirements

Experience in scripting languages such as Perl, Python, or Javascript
BS plus 8 years or MS plus 6 years or PhD plus 4 years in Electrical Engineering or Computer Science
Expertise in timing analysis fundamentals
3+ years doing Static Timing Analysis
3+ years with timing constraint development
Timing analysis using EDA tools such as PrimeTime, Tempus, or others
Understanding of ASIC physical design from RTL to GDSII
Understanding of other sign-off activities including IR/EM, physical verification, DFT

Job Qualifications

Experience in scripting languages such as Perl, Python, or Javascript
BS plus 8 years or MS plus 6 years or PhD plus 4 years in Electrical Engineering or Computer Science
Expertise in timing analysis fundamentals
3+ years doing Static Timing Analysis
3+ years with timing constraint development
Timing analysis experience using EDA tools such as PrimeTime, Tempus, or others
Understanding of ASIC physical design from RTL to GDSII
Understanding of other sign-off activities including IR/EM, physical verification, and DFT
Experience in mentoring, leading and coaching
Expertise developing flows using STA tools such as PrimeTime, Tempus or others
Expertise in ECO flows like PT-DMSA, Tempus-ECO, Tweaker or others
Experience in advanced manufacturing nodes - 16nm or below
Expertise in parasitic extraction tools such as STAR-RC, Quantus or others
Expertise on circuit level analysis using tools like SPICE or SPECTRE
Experience with timing of IO interfaces like DDR, HBM, PCIe, Die-to-Die

Job Duties

Develop and maintain flows for block and full-chip level static timing analysis
Write, debug and validate timing constraints for blocks and full-chip
Run Static Timing Analysis and provide frequent feedback to team members and leads
Provide guidance on fixing timing issues including generating ECOs and fixing constraint issues
Develop scripts to automate running timing analysis and generate reports
Collaborate and work effectively as part of a start-up like team with other physical design engineers and RTL/architecture teams