Pre-Silicon Validation Engineer (Mixed Signal)

Portland, OR, USA|

Job Overview

Compensation

Hourly

Range $44.00 - $73.00

Benefits

Health Insurance

Paid Time Off

Retirement Plan

Professional Development

flexible schedule

Job Description

USM Business Systems Inc. is a rapidly growing global System Integrator, Software and Product Development, IT Outsourcing, and Technology Solutions provider headquartered in Chantilly, VA, with offshore delivery centers in India. Since its establishment in 1999, USM has built a strong reputation for delivering world-class quality and services through industry best practices designed to provide exceptional value to its clients. The company specializes in a broad array of IT solutions including technology innovation, ERP and CRM consulting, Product Engineering, Business Intelligence, Data Management, SOA, BPM, Data Warehousing, SharePoint Consulting, and IT Infrastructure management. USM also offers custom solutions and services in ERP, CRM, Enterprise Architecture, Offshore Advisory Services, e-commerce, Social, Mobile, Cloud, Analytics (SMAC), and DevOps. Recognized as a certified Minority Business Enterprise (MBE) in the US, USM is considered one of the fastest growing IT Systems Integrators in the Washington, DC metro area. Recently, USM was ranked #9 on the list of top service providers in the DC Metro Area by the Washington Business Journal in 2011. With a project-driven approach, USM consistently fulfills the IT demands of State and Government clients through innovation and business expertise.

The company is seeking a skilled Engineer to join its growing team, focusing on the functional validation of complex products that contain both analog and digital components. This role involves using digital and mixed signal simulation tools to verify product functionality. The successful candidate will be responsible for defining and developing essential validation infrastructure, including tests, checkers, and occasional scripting using Perl and Unix shell to execute validation plans ensuring design integrity. This position requires deep comprehension of device under test (DUT) specifications, digital logic, and analog circuit implementation. Additionally, the role requires documentation of validation plans and the creation of high-quality technical documentation. Candidates must be adept at understanding and interpreting technical specifications and developing efficient validation strategies and test plans. This position offers an exciting opportunity to work at the intersection of analog and digital technology within a dynamic and expanding IT services environment. Candidates will be part of a forward-thinking team that leverages cutting-edge simulation and verification methodologies in the delivery of superior technology services.

Job Requirements

BS or MS in electrical engineering, computer engineering, or electrical and computer engineering
Minimum 2 years experience with analog and mixed signal circuits
Minimum 2 years experience with digital logic design and simulation using Verilog or VHDL
At least 1 year experience in developing verification collateral using SVTB based OVM or UVM or Verilog/VHDL
Experience with high speed IOs such as DDR, PCI-express, or USB
6 months experience with computer architecture
6 months experience with scripting languages like Perl or Shell
6 months experience with circuit simulation tools like Pspice
Minimum 2 years experience with UNIX or Linux

Job Qualifications

BS or MS in Electrical Engineering, Computer Engineering, or Electrical and Computer Engineering
2 years experience with basic analog and mixed signal circuits
2 years experience with digital logic design and simulation using Verilog/VHDL
1 year experience in developing verification collateral using SVTB based OVM/UVM or Verilog/VHDL
1 year experience with high speed I/Os like DDR, PCI-express, USB or similar IO interfaces
6 months experience with computer architecture
6 months experience with scripting languages like Perl or Shell
6 months experience with circuit simulation tools like Pspice and application of circuit analysis concepts
2 years experience with UNIX or Linux
6 months or more experience with Verilog-A/VHDL-A/AMS and mixed signal simulation tools like Cadence AMS, Mentor ADMS or their equivalent (preferred)
6 months or more industry experience in SOC/ASIC verification (preferred)
6 months or more experience in post-silicon debug and validation (preferred)
Working knowledge of C/C++/System C and other high-level languages (preferred)

Job Duties

Functional validation of products with both analog and digital components using digital and mixed signal simulation tools
Defining and developing validation infrastructure including tests, checkers, and scripting in Perl or Unix shell to execute validation plans
Reading and interpreting technical specifications to create high-quality technical documentation
Understanding device under test (DUT) specifications, digital logic, and analog circuit implementation
Defining validation strategy and creating test plans
Documenting validation plans and creating appropriate software/content to execute the plan